A conventional method pertinent to the above general field of the invention is known from U.S. Pat. No. 6,204,098, wherein dielectrically insulated islands are produced on an SOI substrate. The insulated islands are filled by epitaxially grown material, whereby the active silicon layer of the SOI wafer serves as a seed for the growth. Through such a process, only insulated islands having the same height or thickness can be produced. An active layer within these islands has a first relatively large thickness. According to FIG. 6 of the cited patent reference, complementary MOS transistors are formed in the islands, and vertical DMOS transistor cells are formed outside of the islands. The vertical DMOS transistor cells are shallower than the dielectrically insulated wells. Furthermore, the vertical DMOS transistor cells are not dielectrically insulated relative to the substrate.
European Patent Application Publication EP 1 049 156 A1 discloses a structure in which a trench is surrounded with an oxide. The trench is filled through an epitaxial lateral overgrowth (ELO) process with the use of a seed, which was formed in the bottom or floor of the trench by opening the oxide layer. Thereafter, the seed opening is closed through a trench. This a rather complicated and space-consuming structure.
In the context of a conventionally known bipolar-CMOS-DMOS (BCDMOS) technology, it is known to provide integrated circuits and their associated fabrication methods, whereby high voltage DMOS capabilities are combined with low voltage CMOS and bipolar characteristics on a single chip. A voltage value of 5 V is a typical example of a low voltage in this context, while a high voltage in this context refers to voltage values up to more than 100 V. DMOS transistors find application as high voltage components, whereby the high voltage can be applied between the drain region and the source region of the transistor.
For future concepts and designs within the field of the BCDMOS technology, it is absolutely necessary to better take into account the special requirements of both the CMOS region (e.g. low leakage currents) as well as the DMOS region (e.g. high power, high dielectric strength, high thermal dissipation, etc.). In order to avoid power losses in the CMOS part due to leakage currents, and to prevent parasitic capacitances, and thereby among other things to improve the performance characteristics of the transistors, it is necessary to provide layer thicknesses in the range of approximately 200 nm when using silicon as the semiconductor material. This, however, is contrary to the requirements and demands for so-called smart-power-elements based on DMOS technology with high dielectric strength and good thermal dissipation. Both of these requirements lead to layer thicknesses that are significantly greater than 1 μm.
Contrary to the bipolar technology, in the MOS technologies it is possible to systematically reduce the size of the structures, simply by scaling down the size scale of the various component dimensions. Namely, important electrical characteristics of MOS transistors are not dependent on individual lengths, but rather are dependent on ratios or quotients of the transistor width relative to the channel length. Due to this dependence, in principle, all lengths and widths within a circuit can simply be made smaller by a common or consistent scaling factor k, without thereby changing the electrical characteristics.
However, the scaled reduction of size of components in BCDMOS circuits with vertical SOI insulation is limited by the above mentioned mutually contrary requirements. In order to minimize leakage currents at high temperatures, the active silicon thickness in the CMOS part should be very thin, so that the source and the drain lie on the buried oxide. On the other hand, the active silicon layer in the DMOS drift region should be thicker in comparison, in order to increase the voltage withstand characteristic or dielectric strength.